This invention relates to high speed peak detection, and more particularly to a CMOS-based peak detector for finding signal minimums and maximums, e.g., glitches, on a signal during the intervals between successive high speed samples in a fast-in, slow-out data acquisition system.
U.S. Pat. No. 4,271,488 to Saxe for a "High-Speed Acquisition System Employing an Analog Memory Matrix", hereby incorporated by reference, disclosed one version of a high speed analog data acquisition system. Co-pending patent application Ser. No. 07/589,222 by Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, describes an improved analog signal acquisition system that is faster than the system described in the '488 patent.
Any method for determining the behavior of an analog signal that is based on sampling the signal at discrete intervals faces the fundamental issue of uncertainty as to the behavior of the signal between samples. The behavior of the signal between samples may nonetheless be of great interest, e.g., if there are glitches on the signal that are causing some sort of problem.
There are digital methods for finding the minimum and maximum behavior of an analog signal, but they also leave gaps between samples and the behavior of the signal within those gaps is still undetermined. However, if the signal can be sufficiently oversampled to ensure capture of the transient events of interest, such approaches can appear to be continuous relative to lower bandwidth activity. In one of these digital methods, two registers are used to store the output of an analog-to-digital converter. A digital comparator monitors the contents of the two registers and retains, for example, the larger value, while enabling the other register to store the next incoming sample. For a "max" detector, the smaller sample is always discarded and the larger one retained. Thus, the largest value received so far is always saved in one register, while the other register is made available for storing the next incoming value. The result is that the largest value found during a sampling period ends up stored in one or the other of the two registers at the end of the period and that register is then selected for readout. Speed increases can be achieved by interleaving several such max (or min) monitors and selecting the most extreme of their outputs as the maximum-max at the end of the sampling period. However, for high frequency signals and/or very fast transients sufficient oversampling is either technically infeasible or prohibitively expensive.
In analog data acquisition systems implemented using analog circuitry and bipolar transistors and diodes there is a convenient way to determine signal minimums and maximums. A diode and capacitor can be arranged to store the largest voltage signal that appears on the input within a sample interval. Using two such diode/capacitor circuits in alternation, one can be used to monitor the signal while the other is being read out and cleared to prepare it for its turn at monitoring the signal.
Complementary Metal Oxide on Semiconductor (CMOS) transistor technology provides some advantages over bipolar transistor technology. In particular, circuitry implemented in CMOS is less expensive, more dense, and uses less power than comparable circuitry implemented in bipolar transistors. However, MOS transistors are slower than bipolar ones, and must be configured differently in order to achieve high bandwidth operation.